`timescale  1ns/1ns           
module Can_BUS( 
                   iClk ,                   
                   iRst_n        ,                       
                   i_mpc_intr_n   ,                                               
                   i_can_data  ,                      
                   i_miso      ,                                                                
                   o_can_data  ,  			   
                   o_sck       ,                      
                   o_mosi      ,                      
                   o_ssn       ,
                   iM_S_slect,
				   o2515Reset				   
				   );                          
//input ports 
input          iClk ;          
input          iM_S_slect ;                                        
input          iRst_n     ;                                                
input          i_mpc_intr_n;  //对端发缓冲为空，接缓冲已满，产生中断                                                
//input frame data                                                        
input  [ 63:0]  i_can_data   ;  //输入数据                                          
//from MPC2515                                                            
input           i_miso       ;              
//output ports                                                                                                                                                   
output [ 63:0]   o_can_data  ;  //输出数据                                            
//translate to MPC2515                                                    
output          o_sck  ;                  
output          o_mosi ;                 
output          o_ssn  ; 
output o2515Reset;                  
//internal wires
wire         intr;
wire         intr_2;
//wire         rfempty ;  
wire  [7:0]  spi2pci_data;
wire  [7:0]  spi2pci_data_2;
wire         sel;        
wire         we;      
wire  [1:0]  addr;      
wire  [7:0]  tx_data ;  
wire  [4:0]  work_state; 
wire  [7:0]  init_state;  
wire         wsettcnt_flag; 
wire         iClk;
wire         iRst_n;

reg  [ 63:0]  r_can_data   ;  
reg  [ 7:0]  r_can_data_2   ;  
reg  [4:0]   r_DataCount,r_DataCount_2;             
pcispi_link  U_pcispi_link_inst(
           .iClk          (iClk          ),                                  
           .iRst_n            (iRst_n            ),                     
           .i_mpc_intr_n     (i_mpc_intr_n  ),                               
           .i_intr           (intr             ),                                         
           .i_can_data       (i_can_data       ),  
           //.i_can_data       (r_can_data       ),                              
           .i_rx_data        (spi2pci_data     ),                               
           .o_sel            (sel              ),                               
           .o_wr_en          (we               ),                               
           .o_addr           (addr             ),                               
           .o_tx_data        (tx_data          ),                                                          
           .o_can_data       (o_can_data       ),                               
           .o_work_state     (work_state       ),                               
           .o_settcnt_flag   (wsettcnt_flag     ),
           .iM_S_slect       (iM_S_slect       ),
		   .o2515Reset		 (o2515Reset)
          );
 
spi_interface U_inst(
       .iClk     (iClk),      
       .iRst_n       (iRst_n  ),        
       .i_sel       (sel         ),        
       .i_addr      (addr        ),       
       .i_we        (we          ),         
       .i_data      (tx_data     ),       
       .i_work_state(work_state  ), 
       .i_settcnt_flag(wsettcnt_flag),
       .o_data      (spi2pci_data),       
       .o_inta      (intr        ),        
       .o_sck       (o_sck       ),        
       .o_mosi      (o_mosi      ),       
       .i_miso      (i_miso        ),  
       .o_ssn       (o_ssn       )     
       );



//测试帧数据
always@(posedge iClk or negedge iRst_n)       
  if(~iRst_n) begin                               
    r_can_data <=63'd0;
    r_DataCount<=5'd0;
   end                                                
  else begin   
	r_can_data<=r_can_data+10;	
    end	

endmodule



























